A conventional integrated circuit contains a plurality of patterns of metal lines separated by inter-wiring spacings and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the metal patterns of vertically spaced metallization layers are electrically interconnected by vias. Metal lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type, according to current technology, may comprise eight or more levels of metallization layers to satisfy device geometry and micro-miniaturization requirements.
A commonly used method for forming metal lines and vias is known as “damascene.” Generally, this process involves forming an opening in the dielectric interlayer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After an opening is formed, the opening is filled with copper or copper alloys to form a via or a trench. Excess metal material on the surface of the dielectric interlayer is then removed by chemical mechanical polishing (CMP).
Copper has replaced aluminum to form metal lines because of its lower resistivity. However, copper suffers from electro-migration (EM) and stress-migration (SM) reliability issues as geometries continue to shrink and current densities increase.
FIG. 1 illustrates a cross-sectional view of a conventional interconnect structure 1 formed using damascene processes. Metal lines 2 and 4, which are typically formed of copper or copper alloys, are interconnected by via 10. Inter-metal-dielectric (IMD) 8 separates the two layers where metal lines 2 and 4 are located. Etch stop layer (ESL) 5 is formed on copper line 2. Diffusion barrier layers 12 and 14, which typically comprise Ta or TaN, are formed to prevent copper from diffusing into surrounding materials. ESL 5 typically has a higher dielectric constant (k value) than low-k dielectric layer 6 and IMD 8. As a result, the parasitic capacitances between the metal lines are undesirably increased.
FIG. 2 illustrates an alternative interconnect structure 3. Metal cap 16 is formed on copper line 2. Metal cap 16 is typically formed of materials not prone to electro-migration and stress-migration. This layer improves the reliability of the interconnect structure by reducing copper surface migration. It has been found that under stressed conditions, the mean time to failure (MTTF) of interconnect structure 3 is significantly longer than that of interconnection structure 1. With metal cap 16, the stress-induced void formation is also significantly reduced. Additionally, the parasitic capacitances are also reduced.
Since metal cap 16 is typically formed only on copper line 2, weak points exist at the interface of metal cap 16 and diffusion barrier layer 14, and copper may still diffuse out from these weak points.
Alternatively, metal cap 16 may be formed by soaking copper in silane (SiH4) in a thermal and non-plasma ambient. Copper silicide is thus formed on the surface of copper line 2. A drawback of such a scheme is that during silane soaking, silicon in the silane will diffuse deep into copper line 2, causing copper silicide's formation deeply in copper line 2. As a result, the resistivity of copper line 2 is increased. The problem becomes worse when advanced technologies are used to form integrated circuits, and thus the thickness of copper line 2 is reduced.
The conventional schemes for forming cap layers have advantageous features and disadvantageous features, and thus may be used accordingly for different design requirements. To satisfy different design requirements and improve the reliability of integrated circuits, more methods for forming cap layers on copper lines are needed.